Synchronization is a requirement in many power systems and power electronics applications that require monitoring and control of a device or system. The synchronization information which includes frequency, amplitude, and phase angle with respect to a reference frame are typically used in control applications to improve the supply of the electric power to the end users. The synchronization information must also be capable of being immune to harmonics, inter-harmonics, wideband stationary/non-stationary noise, and notch-type disturbances.
The need for synchronization information is not restricted to utility networks where frequency is 50/60 Hz with a range of ±5 Hz. The need also expands to non-utility applications such as the aerospace industry where the frequency is 400 Hz and can vary in the range of 360-800 Hz.
There are currently a number of methods for the extraction of synchronization information. Five of these existing methods are described below with reference to several of the following documents, which are incorporated herein by reference:    [1] A. Karimi-Ziarani, “Extraction of Non-stationary Sinusoids,” Ph.D. Thesis, University of Toronto, Toronto, Canada, 2002;    [2] M. Karimi-Ghartemani, “A Synchronization Scheme Based on an Enhanced Phase-Locked Loop System”, Ph.D. Thesis, University of Toronto, Toronto, Canada, 2004;    [3] M. Karimi-Ghartemani, and A. Karimi-Ziarani, “Periodic orbit analysis of two dynamical systems for electrical engineering applications”, Journal of Engineering Mathematics, Volume: 45, Number: 2, pp. 135-154, February 2003;    [4] S. Pavljasevic, “Synchronization to Disturbed AC Utility Network Signals in Power Electronics Applications”, Ph.D. Thesis, University of Toronto, Toronto, Canada, 2002;    [5] B. P. McGrath, D. G. Holmes, and J. Galloway, “Improved Power Converter Line Synchronization Using an Adaptive Discrete Fourier Transform (DFT)”, Power Electronics Specialists Conference, pesc, IEEE 33rd Annual, Volume: 2, Pages: 23-27, 23-27 Jun. 2002;    [6] S. K. Chung, “A phase tracking system for three phase utility interface inverters”, Power Electronics, IEEE Transactions on, Volume: 15, Issue: 3, Pages: 431-438, May 2000;    [7] S. K. Chung, “Phase-locked loop for grid-connected three-phase power conversion systems”, Electric Power Applications, IEE Proceedings, Volume: 147, Issue: 3, Pages: 213-219, May 2000;    [8] L. N. Arruda, B. J. Cardoso Filho, S. M. Silva, S. R. Silva, and A. S. A. C. Diniz, “Wide bandwidth single and three-phase PLL structures for grid-tied PV systems”, Photovoltaic Specialists Conference, Conference Record of the Twenty-Eighth IEEE, Pages: 1660-1663, 15-22 Sep. 2000;    [9] S. J. Lee, J. K. Kang, and S. K. Sul, “A new phase detecting method for power conversion systems considering distorted conditions in power system”, Industry Applications Conference, Thirty-Fourth IAS Annual Meeting, Conference Record of the 1999 IEEE, Volume: 4, Pages: 2167-2172 vol. 4, 3-7 Oct. 1999;    [10] Data sheet, “MC14046B, Phase Locked Loop”, Motorola, http://www.onsemi.com/home;    [11] Application notes, “Configuring and Applying the MC74HC4046A Phase-Locked Loop”, Motorola, http://www.onsemi.com/home;    [12] M. K. Fellah, J. F. Aubry, P. Wan, and C. Zanne, “Digital synchronization system for the control of self-controlled synchronous machine converters”, CRAN, Groupe, AUREL, ENSEM-INPL, 2, Avenue de la foret de Haye, 54516, Vandoeuvre-Les-Nancy, France;    [13] American National Standard, ET1.523-2001, available at http://www.its.bldrdoc.gov/projects/devglossary;    [14] TMS320C31 User's Guide, Texas Instruments, Literature number: SPRU031E 2558539-9761 revision L, July 1997; and,    [15] Development Kit User Guide, “Manual Number: NT107-0132”, Nallatech, Issue: 9, 2003, available at http://www.nallatech.com.
Enhanced Phase Locked Loop. The algorithm introduced in [1] and [2] is based on a phase locked loop (PLL) architecture and determines the amplitude, phase angle, and frequency of the dominant component of an input signal. The mathematical relations require knowledge of constant values (μ1, μ2, and μ3) that determine the gains for different operations such as the integrator modules in the algorithm. The choice of μ1, μ2, and μ3 is critical in terms of influencing the performance of the algorithm and is typically optimized for a pre-selected operating point, i.e. 60 Hz. Moreover, μ1, μ2, and μ3 do not maintain the optimized values as the frequency of the dominant component changes. The algorithm performance depends on the choice of μ1, μ2, and μ3. For instance, a larger μ1 results in a faster response time while degrading the resolution of the EPLL. An approximate assessment of the algorithms performance is summarized below based on the information provided in references [1-3]: a nominal frequency of 50/60 Hz; a frequency range of 20-120 Hz; and, a transient response time of 6 cycles based on the nominal frequency value.
Multirate Phase Locked Loop. A digital implementation of the synchronization system based on a multirate phase locked loop (MPLL) is provided in [4]. The MPLL operates with two different sampling rates. One sampling rate is called fast sample rate (v) and is higher than the input signal frequency. The other is equal to the input signal frequency and is referred to as the slow sample rate (f). The slow sample rate is related to the fast sample rate by
                              N          =                      v            f                          ,                            (        1        )            where N is the number of samples per cycle. During the time the input signal frequency changes, a PLL error is generated that consequently changes the fast sample rate accordingly and hence the MPLL achieves phase synchronization. The response time of the MPLL to a 1 Hz step frequency perturbation exceeds 600 msec (over 36 cycles of a 60 Hz signal). Furthermore, the response time is in the order of seconds for a 4 Hz step frequency change from 60 Hz to 64 Hz. The long delay time is a direct result of the tradeoff that exists between the dynamic response and noise immunity of the MPLL. A performance summary of the algorithm is provided below: a nominal frequency of 50/60 Hz; a frequency range of 48-72 H; and, a slow response time in the order of seconds.
Adaptive Fourier Transform for Synchronization. The study presented in reference [5] considers zero crossing synchronization for power converter applications using a recursive digital Fourier transform (DFT). The recursive DFT approach causes phase differences due to mismatches between the DFT time window and the system period. This method achieves a faster response time to frequency or phase transients than the MPLL [4] and EPLL [3]. A performance summary of the algorithm based on the data provided in references [5] follows: a nominal frequency of 50/60 Hz; a limited frequency range of approximately ±10 Hz for a 50/60 Hz utility system; and, a transient response time of approximately 4 cycles of the nominal frequency.
Three-Phase Phase Locked Loop. A three-phase PLL method for a balanced three-phase system that consists of a phase detector and a loop filter is reported in [6-8]. The phase detection is designed using a dq-transformation frame. The loop filter consists of a PI regulator that generates a phase error employed by a voltage controlled oscillator (VCO). The design of the loop filter involves a trade off between the dynamic performance and filtering of undesired distortion on the input signals. The loop filter requires a low bandwidth to become effective in filtering input signals superimposed with harmonics and/or DC-offset. The low bandwidth results in a poor dynamic response. In the presence of a voltage unbalance on the three-phase utility lines, a positive sequence detector is combined with the three-phase PLL that can eliminate the effects of unbalance [9]. The positive sequence detector employed in [9] is not frequency adaptive and hence can only operate over a limited frequency range. The performance of the three-phase PLL is summarized as follows: poor dynamic response due to a low bandwidth implementation of loop filter; and, lack of frequency adaptability.
Analog Phase Locked Loop. Another method for phase synchronization is to use an analog phase locked loop (PLL). This scheme is available in the form of integrated chips from Motorola, among other manufacturers [10, 11]. The shortcomings of the analog PLL are as follows: Inability to synchronize to disturbed signals; typically a high order front-end filter is required to alleviate this concern but the filter is complex and is subject to temperature drift and component tolerances. In addition, a high order filter introduces long delay times and gives rise to a slow transient response, inability to perform frequency tracking, and sensitivity to online noise.
In view of the foregoing disadvantages, there exists a need for an improved synchronization method and system for power systems.